1. Field
This disclosure relates to the field of data processing systems. More particularly, this disclosure relates to the field of the translation between memory transactions of a first type and memory transactions of a second type within a data processing system.
2. Description
It is known to provide data processing systems in which memory transactions are routed across an interconnect between masters and slaves. Within such systems it is known to provide a system memory management unit which is able to translate memory transactions addresses, and associate programmable memory attribute data, for memory transactions passing across the interconnect circuitry. Such a system memory management unit may read page table data stored within the memory address space in order to control the translations made and the attributes applied. As such page table data can be slow to access, it is known to provide a translation lookaside buffer, or buffers, within system memory management units for caching translation data and attribute data in order to improve the speed of operation.
One issue with such an approach is that as the number of transaction sources and transaction destinations increases and the volume of transactions increases, the translation lookaside buffer(s) may be too small. One way of addressing this problem is to provide local translation lookaside buffers (or address translation caches) within the bus masters associated with the system such that these may perform their own address translations without requiring address translations to be supported by the system memory management unit, and the finite resources of the translation lookaside buffer of the system memory management unit.
It is also known to provide data processing systems which include bridge circuitry serving to bridge between memory transactions of a first type and memory transactions of a second type. For example, one side of the bridge circuit may utilise memory transactions in accordance with the PCI Express format and the other side of the bridge circuit may utilise memory transactions in accordance with the AMBA AXI transaction format. A problem that can arise in translating between memory transactions of a first type and memory transactions of a second type is that attribute data associated with memory transactions of a first type may not be supported, and have no counter part within, memory transactions of the second type. Accordingly, if a bus master issuing memory transactions of the second type wishes these to be translated into memory transactions of the first type without calling upon the system memory management unit to look up the memory attributes for the memory transaction of the first type, then the memory transaction of the second type has a difficulty that it has no conventional way of indicating attributes to be used when the translation is made into a memory transaction of the first type. One way of dealing with this would be to apply a default set of attributes when such a translation is made, but this lacks flexibility and is unable to deal effectively with all the desired different types of memory transaction that it may be wished to pass through the bridge circuitry.